1. Field of the Invention
The present invention relates to source-synchronous type data reception and particularly to a memory control apparatus and a mask timing adjusting method.
2. Description of the Related Art
A Double Data Rate Synchronous Dynamic Random Access Memory (DDR-SDRAM) performs a write operation and a read operation by using a bi-directional data bus and a strobe signal. In the read operation, a required number of sets of strobe edges (rise and fall edges) are outputted following a high-impedance state (“Hi-Z state”) and a “preamble” state of the strobe signal. Finally, the strobe signal returns to the Hi-Z state after a postamble state. A read data receive circuit needs to detect the preamble state and capture a strobe signal edge as a clock for data reception.
For example, Patent Document 1 discusses a snap-shot data training method for determining the optimum timing of a DQS enable signal in a single read operation. A sequence of Gray code counts is first written into a memory and then read in a single burst. A controller samples the read burst at a constant interval from the time the command was issued, and determines a loop-around delay. By searching a simple truth table, the optimum DQS enable timing for a normal read is determined. During a normal read operation, it is preferable to sample a counter that is enabled each time a command is issued, by using the first positive edge of the enabled DQS signal. If the counter sample changes, indicating a timing drift, the DQS enable signal can be adjusted to compensate for the variation and maintain a position at the center of the DQS preamble.
Patent Document 2 discusses a receive window position determining method and apparatus. The receive window position determining method involves determining whether a signal to be received within the receive window is within a reduced window within the receive window, the reduced window being shorter in length than the receive window. The shifting of signals to be received within the receive window can be detected early.
Patent Document 3 discusses a memory interface circuit capable of preventing an erroneous operation due to noise by acquiring data using a data strobe signal. A delay circuit delays the data strobe signal DQS and outputs a delay signal. An AND circuit performs a logical AND operation of the delay signal and the data strobe signal DQS and outputs an operation result as a first strobe signal DQSd. The first strobe signal DQSd is inputted into an inverter circuit, which outputs a second strobe signal Ddx complimentary to the first strobe signal DQSd. Based on the first strobe signal DQSd, a first flip-flop latches data DQ, while a second flip-flop latches the data DQ based on the second strobe signal Ddx.
Patent Document 4 discusses a memory controller capable of receiving a strobe signal outputted by a memory correctly as a reception clock regardless of the amount of delay on the board. The memory control apparatus includes a bi-directional buffer capable of turning on or off termination resistors. The resistance values of termination resistors on the pull-up side and the pull-down side can be controlled to be different values. The bi-directional buffer is used for transmission and reception of a strobe signal.
Patent Document 5 discusses an interface circuit for eliminating an unstable operation due to delay variations of a data strobe signal. A control circuit is fed with a read request signal Read_RQ for memory data read and a burst-length information signal BL for the read request. The control circuit controls a pullup circuit such that the data strobe signal DQS is pulled-up when the read request signal Read_RQ is active. Upon detection of transition of the data strobe signal DQS from H level to L level, a mask signal Enable is put in an unmasked state. Upon detection of a repetition of predetermined transitions of the data strobe signal DQS based on the burst-length information signal BL, the mask signal Enable is put in a mask state. By the repetition of such transitions, a postamble of the data strobe signal DQS is started. After the end of the postamble period, the data strobe signal DQS is pulled-up to H level.
However, the timing of input of the preamble is influenced by a wiring delay in the command system (such as clock, CS, RAS/CAS/WE, and address) between the memory control circuit and the memory and a wiring delay in the data system (such as strobe and data buses).
Delay data caused by the memory control circuit or the memory also vary due to voltage or temperature variations, thus affecting the timing of the preamble. Thus, for stable reception of read data, the preamble needs to be detected without being affected by the above causes for variations. If the unstable state of Hi-Z of the strobe signal is captured by the receive circuit, data may be read at a wrong timing or the receive circuit may hang up. Particularly, the problem becomes more serious in higher-speed memory systems, such as DDR2-SDRAM and DDR3-SDRAM.
In the case of Patent Document 1, the preamble state is determined by reading an internal counter that operates by a multiply-by-four clock (where the unit of clock corresponds to the clock inputted into the memory, or a clock with the same frequency), and a Gray code that is written to memory in advance. Patent Document 1 discusses a “training sequence” performed during initial setting, which does not include adjustments for the voltage or temperature variations that may be caused after the initial setting. The technology of Patent Document 1 also requires a clock four times the memory clock.
In the case of Patent Document 2, the receive window corresponds to the period in which the strobe signal is enabled, and the reduced window corresponds to a period between the first valid strobe rise and the last valid strobe fall where a certain relationship between the windows is maintained using a delay and the like. Thus, the problem of capturing the unstable state of the strobe signal during an adjusting procedure is not overcome.
In the case of Patent Document 3, a method is provided for eliminating the unstable state of the strobe signal by using a signal obtained after performing a logic operation between the strobe signal and the delayed strobe signal. Patent Document 3 does not discuss a specific method of dealing with the development of plural edges in an unstable state, nor a method for obtaining a valid period of the strobe signal.
In the case of Patent Document 4, the memory controller may enable the reception of the strobe signal outputted by the memory correctly as a reception clock regardless of the amount of delay on the board. However, the technology is not capable of adjusting the strobe signal accurately on the time axis.
In the case of Patent Document 5, the strobe signal and the mask signal are controlled based on the burst-length information signal indicating the burst length. Thus, the strobe signal cannot be adjusted accurately on the time axis.    Patent Document 1: Japanese Laid-open Patent Publication No. 2009-541868    Patent Document 2: Japanese Laid-open Patent Publication No. 2008-047118    Patent Document 3: Japanese Laid-open Patent Publication No. 2008-250841    Patent Document 4: Japanese Laid-open Patent Publication No. 2009-070150    Patent Document 5: Japanese Laid-open Patent Publication No. 2008-103013